Le microprocesseur 6809

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity test1 is
  port(A : in  std_logic_vector(15 downto 7); 
   SIZE: in  std_logic_vector(1 downto 0);
   E   : in std_logic;
   RW  : in std_logic;
   RAM, ROM, IO0, IO1, IO2, IO3, READ, WRITE : out std_logic);
  ATTRIBUTE LOC : string;
-- Inputs
  ATTRIBUTE LOC OF  A    : SIGNAL IS "1 2 3 4 5 6 7 8 9";
  ATTRIBUTE LOC OF  E    : SIGNAL IS "14";
  ATTRIBUTE LOC OF  RW   : SIGNAL IS "23";
  ATTRIBUTE LOC OF  SIZE : SIGNAL IS "10 11";

-- Outputs
  ATTRIBUTE LOC OF  READ  : SIGNAL IS "22";
  ATTRIBUTE LOC OF  WRITE : SIGNAL IS "21";  
  ATTRIBUTE LOC OF  ROM   : SIGNAL IS "20";
  ATTRIBUTE LOC OF  RAM   : SIGNAL IS "19";  
  ATTRIBUTE LOC OF  IO0   : SIGNAL IS "18";
  ATTRIBUTE LOC OF  IO1   : SIGNAL IS "17";
  ATTRIBUTE LOC OF  IO2   : SIGNAL IS "16";
  ATTRIBUTE LOC OF  IO3   : SIGNAL IS "15";
end;

architecture test1 of test1 is
begin
  process(SIZE)
  variable IO : std_logic := '0';
  begin
  case SIZE is
  -- ROM de 2Ko
  when "00" =>
    ROM <= not (A(15) and A(14) and A(13) and A(12) and A(11));
    IO  := A(15) and A(14) and A(13) and A(12) and  not A(11) and A(10) and A(9);
  when "01" =>
    ROM <= not (A(15) and A(14) and A(13) and A(12));
    IO  := A(15) and A(14) and A(13) and not A(12) and  A(11) and A(10) and A(9) ;
  when "10" =>
    ROM <= not (A(15) and A(14) and A(13));
    IO  := not A(15) and A(14) and  A(13) and A(12) and A(12) and A(11) and A(9);
  when "11" =>
    ROM <= not (A(15) and A(14));
    IO  := A(15) and not A(14) and A(13) and A(12) and A(11) and A(10) and A(9);
    end case;
    IO0 <= not (IO and not A(8)  and not A(7)); 
    IO1 <= not (IO and not A(8) and A(7)); 
    IO2 <= not (IO and A(8) and not A(7)); 
    IO3 <= not (IO and A(8) and A(7));
    RAM <= not(ROM) or not(IO);  -- to /CS of RAM
    WRITE <= not(E and not(RW)); -- to /WE of RAM
    READ  <= not(E and RW);       -- to /CE of ROM

  end process;
end test1;